1. Technical Field
The present invention pertains to electronic devices and systems, and more particularly to an improved method and apparatus for starting up or booting an electronic device such as a data processing system.
2. Description of Related Art
Many devices in use today include electronics that control the operation of at least some portion of the device. While data processing systems are the traditional types of systems that contain such electronics, electronic control is appearing in many other types of devices such as automobiles, telephones and other types of consumer electronics devices, and even home appliances. These types of devices typically have programming code stored within the device that gets executed when the device is initially turned-on or powered-up. This code, and its execution, may be called many different things, such as a boot-up, power-up, start-up or initial program load (IPL) of the device. Some types of systems, such as personal computers, are notoriously slow in providing a ready state after an initial power-up and IPL of the computer.
Many of today's data processing and other types of electronic controlled systems have different types of memory included therein for use by the system. Non-volatile memory, which maintains the value of data stored therein even when there is no power connected to it, is typically used to store the initial start-up or boot code for a data processing system or electronic controlled device. This start-up or boot code is what is executed by a central processing unit (CPU) or controller of the system or device to perform system initialization. This boot code is maintained in non-volatile memory so that the memory contents are maintained even when power is removed from the system or device.
One particular type of non-volatile memory that is used for such boot code is called flash memory. This type of memory device is generally easy to read from, but requires fairly sophisticated control and sequencing of voltage values on various input/output (I/O) pins in order to write/program data into the device.
Volatile memory, such as dynamic RAM (DRAM), is also traditionally contained in a data processing system or electronic controlled device, and is generally used by the CPU or controller as its main or system memory for reading and writing data using traditional memory access techniques.
When the system/device is first powered-up, the system/device is typically designed such that the CPU or controller will begin execution by accessing a boot-up reset vector at a given memory location which contains the starting address of where to begin program execution or sequencing of boot-up code. This boot-up code, also called firmware or internal code, provides functionality to initialize, test and otherwise set-up various system/device aspects, such as initial hardware configuration, etc. and then load an operating or control system into main memory for subsequent execution. In some types of computer systems, this boot code is also known as basic input and output (BIOS) code. Execution control is then passed from the flash memory to system memory for continuing with system initialization and operation by the operating or control system. The reason for partially booting-up using flash memory programming and then transferring control to continue the boot-up sequence from main system memory is that flash memory is much more expensive than main system memory (which is typically comprised of DRAM memory), and therefore system designers want to use as little flash memory in their designs as possible to hold down on costs. Obviously, the more functionality that is provided by the program stored in flash memory, the larger the size (and associated cost) of flash memory that will be required by the system/device.
Cache memory, which is typically comprised of high-speed static RAM (SRAM) devices, is also generally provided in a data processing system for holding instructions and/or data that are likely to be accessed in the near term by a CPU or controller. Because CPUs/controllers have increased in operating speed at a much faster pace than RAM as technology has progressed, without adequate system design, a CPU/controller could waste much of its time waiting to obtain instructions or data from memory, rather than performing calculations. One of the fastest types of RAM, Static RAM (SRAM), is generally too expensive to use for all of system's memory needs. As a compromise, computers generally come with a relatively small amount of SRAM that is used as cache memory. If a CPU instruction or data stored in cache is required again, the computer can access the cache for the instruction/data rather than having to access the relatively slower DRAM. Since the cache memory is organized more efficiently, the time to find and retrieve information is reduced and the CPU is not left waiting for more information. Many CPUs/controllers have two types of cache: level 1 and level 2. Level 1 (L1) cache has a very fast access time, and is typically embedded as part of the CPU/controller integrated circuit device itself. Level 2 (L2) is typically situated near, but separate from, the CPU/controller and has an interconnecting bus to the CPU/controller. Modern CPUs/controllers may also have both L1 and L2 caches integrated into the devices. Some systems also have a separate instruction cache and data cache.
Prefetching is another technique for improving the overall performance of a data processing system. For example, instead of only reading a next instruction from memory for execution by a CPU/controller, an instruction prefetch unit can monitor the instruction stream being executed by the CPU/controller and make educated guesses as to which instructions stored in main system memory are likely to be executed in the future, and thus should be prefetched into the instruction cache so that they are already there in high-speed cache and ready to be read by the CPU/controller (thus avoiding delays or latency that would otherwise occur if the instruction/data were not fetched until actually being called-for by the CPU/controller). One way to make these educated guesses for instruction prefetching is to monitor the instruction stream for instructions that cause execution to occur non-sequentially, such as a conditional JUMP instruction, and predict which condition will exist when the instruction is actually executed to thereby prefetch any non-sequential instructions in the predicted path. If there are no instructions that would cause the instruction stream to deviate from its current sequential execution, then the next n instructions in the sequentially executed data stream can be prefetched into the instruction cache. These types of instruction prefetching, as well as similar techniques for prefetching of data, are commonly known to many hardware and system designers.
These types of instruction and data prefetching are very common for systems where a program to be executed has been loaded into general usage system memory such as DRAM. However, in certain situations such as when executing boot-up or IPL code out of flash memory, some systems inhibit instruction or data prefetching into cache by running in a cache-inhibit mode. This may occur, for example, if the cache line size is different from the size of an interconnecting bus. By running in a cache-inhibited mode, where instructions and data cannot be cached and prefetched, access latencies occur each time a new instruction or data is accessed and there is a significant impact in the performance of the system. As this cache-inhibit mode is typically done for certain systems when they are executing their boot-up code out of flash or other type of non-volatile memory, the system initial-program load (IPL) or boot-up time is greatly increased. This increase in boot time is not only an annoyance to end-users, but also to test engineers and/or technicians as it increases the time required to boot-up and test a device, thus generally slowing down the overall efficiency for manufacturing such systems and devices.
It would thus be desirable to provide an improved method, apparatus and program product that would mitigate this inability to use a cache for prefetching during system/device IPL or boot-up.